In order to optimize the code generation for the RISC processors which (in most cases) have a concept of delayed branches a special optimization phase for the PSL compiler was build to fill the delay slots. This new compiler phase is called lapopt. It collects several optimizations which work on the generated stream of instructions (the lap code). This optimization phase is enabled by default, it is controled by the switch lapopt, and it can be turned off and on by
A sample of optimized code can be found in the following section on disassemble.